Virtually all modern MOS and bipolar integrated circuits use the local oxidation of silicon (LOCOS) technique to develop regions which will laterally isolate the devices on the integrated circuit. This isolation structure is typically formed by ion-implantation doping of the field region, followed by the local growth of the thick field oxide. The active device regions are protected during these steps by masking layers of silicon nitride which are subsequently removed.
Unfortunately, the LOCOS process results in the lateral oxidation of the silicon underneath the nitride mask, forming the so-called "bird's beak effect". This effect is graphically illustrated in FIGS. 1 and 7 of U.S. Pat. No. 4,551,910. Since the "bird's beak" is insufficiently thick to form effective isolation, but sufficiently thick to prevent the formation of an active device where it is located, it reduces the effective device area and becomes one of the limiting factors in achieving high packing density for very large scale integrated circuits.
It has long been recognized in the prior art that it is desirable to reduce the bird's beak to minimize the transition regions between active areas. Other isolation technologies have been proposed as alternatives for LOCOS. For example, the side wall masked isolation (SWAMI) technique has been proposed which involves the addition of a second nitride layer on the side wall. See FIG. 2, p. 226, of K. Y. Chiu et al., "The SWAMI--A Defect Free and Near-Zero Bird's-Beak Local Oxidation Process and Its Application in VLSI Technology," IEDM 82 (International Electron Device Meeting, 1982), Sec. 9.3, pp. 224-227 (1982). Thus U.S. Pat. No. 4,477,310 shows the use of nitride layers on the side wall of active regions. However, fully recessed field oxide layers are formed from an unmasked silicon substrate.
Still another method described is the so-called sealed interface local oxidation (SILO) technique which uses three layers of nitride over silicon followed by an oxide layer and a cap nitride layer. See FIG. 1, p. 223, of J. Hui et al., "Electrical Properties of MOS Devices Made With SILO Technology," IEDM 82, Sec. 9.2, pp. 220-223 (1982).
Also, the buried oxide (BOX) technique has been devised which uses an aluminum mask to etch a silicon groove and the subsequent removal of a plasma deposited silicon dioxide layer. See FIG. 1, p. 386, of K. Kurosawa et al., "A New Bird's-Beak Free Field Isolation Technology for VLSI Devices," IEDM 81, Sec. 16.4, pp. 384-387 (1981). Still another technique involves the selective polysilicon oxidation using three layers of silicon dioxide over silicon followed by a polysilicon and cap nitride; see FIG. 1, p. 566, of J. Matsunaga et al., "Selective Polysilicon Oxidation Technology for Defect Free Isolation," IEDM 80, Sec. 22.4, pp. 565-568 (1980).
Unfortunately, the SILO technique is not fully effective because of contamination and defects at the silicon/nitride interface which cannot be easily controlled. The SWAMI and BOX techniques are far too complicated, the BOX technique requiring several masking steps to achieve good planarity. The selective polysilicon oxidation (SEPOX) technology causes reentrant corners at the field oxide edges.
Other prior art relating to the formation of dielectric isolation for integrated semiconductor devices include U.S. Pat. No. 4,582,565 to Kawakatsu which employs a trench isolation technique. In this structure the silicon substrate is disturbed by virtue of the formation of the trench and requires the deposition of insulating layers on the lengthy vertical surfaces of the trench. Long narrow trenches are difficult to fill completely. The resulting tendency to form voids is well known. In addition, a planar-type structure is formed.
Kahng U.S. Pat. No. 4,271,583 shows a process for forming a planar structure with fully recessed oxide isolation regions. In addition, in the anisotropic etching step, the silicon dioxide layer 23 lies adjacent to a portion of the substrate 13 which is subject to oxidation. This procedure allows the diffusion of oxygen laterally through the layer 23, thereby reducing the device area of the structure.
Rogers et al. U.S. Pat. No. 4,571,819 recognizes the difficulty of forming trench isolation oxides, particularly the problem of void formation. The field oxide is deposited by low pressure chemical vapor deposition, a technique which does not produce a high quality field oxide. In addition, the process shown is cumbersome, since the voids formed in the oxide must be eliminated by a melting and reflowing process.
Ko U.S. Pat. No. 4,472,873 shows a typical recesses LOCOS process. FIG. 1C shows the formation of the so-called "bird's beak" which is aggravated by the presence of the silicon oxide layer 14b adjacent to the edges 13a and 13b which are to be oxidized.
Han et al. U.S. Pat. No. 4,407,696 also shows an approach to eliminate the problem of the bird's beak effect in the fabrication of isolation oxidation regions for MOS circuits. In this procedure, the initial oxidation region shown has extensive bird's beak, largely resulting from the lateral migration of the oxygen along the stress release layer 26. To reduce the bird's beak, an extra etching step is required to redefine the oxidation region.